Asic soc functional design verification

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asic soc functional design verification

Ashok B. Mehta (Author of ASIC/SoC Functional Design Verification)

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Published 09.12.2018

Verification IP – Trends and Technology for FPGA and ASIC Design Verification

ASIC/SoC Functional Design Verification

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This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. Springer Professional. Back to the search result list. Table of Contents Frontmatter Chapter 1. Introduction Abstract.

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Springer June The logical consequence of this parameter variation is that circuit characteristics, as delay and power, also become random variables., Ashok B Mehta Published in Chapter 1.

It seems that you're in Germany. We have a dedicated site for Germany. This book describes in detail all required technologies and methodologies needed to create a comprehensive, functional design verification strategy and environment to tackle the toughest job of guaranteeing first-pass working silicon. The author first outlines all of the verification sub-fields at a high level, with just enough depth to allow an engineer to grasp the field before delving into its detail. Springer June

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4 thoughts on “Ashok B. Mehta (Author of ASIC/SoC Functional Design Verification)

  1. A Comprehensive Guide to Technologies and Methodologies. Ashok B. Mehta. SystemVerilog Assertions (SVA).

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